1. Field of the Invention
The present invention relates to a semiconductor memory device and a semiconductor testing method, and more specifically to a semiconductor memory device having a test mode and a semiconductor testing method utilizing the same.
2. Description of the Background Art
FIG. 9 is a circuit block diagram representing the arrangement of a conventional dynamic random access memory (hereinafter referred to as a DRAM) 30. Such a DRAM 30 is disclosed, for instance, in Japanese Patent Laying-Open No. 6-295599.
In FIG. 9, DRAM 30 is provided with an address buffer circuit 31, a control signal generating circuit 32, a memory portion 33, selectors 34 and 40, a data input buffer 35, a comparison data register 36, a determination circuit 37, a gate circuit 38, a determination result register 39, and a data output buffer 41.
Address buffer circuit 31 generates row address signals RA0 to RAn, column address signals CA0 to CAn, and block selecting signals B0 and B1 based on external address signals A0 to An (n is an integer greater than or equal to 0). Address signals RA0 to RAn and CA0 to CAn are provided to memory portion 33, and block selecting signals B0 and B1 are provided to selector 34. Control signal generating circuit 32 operates in synchronism with an external clock signal CLK, generates a variety of internal control signals according to external control signals /RAS, /CAS, /WE, /OE, and /CS, and controls the entire DRAM 30.
Memory portion 33 includes four memory blocks 33a to 33d, and stores one bit of data or four bits of data from selector 34 during a write operation, and reads four bits of data and provides the data to selector 34 and determination circuit 37 during a read operation.
Memory block 33a includes a memory array 42, a sense amplifier+input/output control circuit 43, a row decoder 47, and a column decoder 48, as shown in FIG. 10. Memory array 42 includes a plurality of memory cells MC arranged in a matrix of rows and columns, a word line WL provided corresponding to each row, and a bit line pair BL and /BL provided corresponding to each column. Each memory cell MC is of the well known type which includes an accessing N-channel MOS transistor and a capacitor for storing information.
Sense amplifier+input/output control circuit 43 includes a data input/output line pair IO and /IO, a column select line CSL provided corresponding to each column, a column select gate 44, a sense amplifier 45, and an equalizer 46. Column select gate 44 includes a pair of N-channel MOS transistors connected between bit line pair BL and /BL and data input/output line pair IO and /IO. Each N-channel MOS transistor has a gate connected to column decoder 48 via column select line CSL. When column decoder 48 raises column select line CSL to the logic high or "H" level or the selected level, a pair of N-channel MOS transistors are rendered conductive, coupling bit line pair BL and /BL to data input/output line pair IO and /IO.
Sense amplifier 45 amplifies the small potential difference between bit line pair BL and /BL to a power-supply voltage VCC according to sense amplifier activating signals SON and ZSOP respectively attaining the "H" level and the logic low or the "L" level. Equalizer 46 equalizes the potentials of bit line pair BL and /BL to a bit line potential VBL (=VCC/2) according to a bit line equalizing signal BLEQ attaining the active level or the "H" level.
Now, the operation of memory block 33a shown in FIG. 10 will be described. During a write operation, column decoder 48 raises to the selected level or the "H" level column select line CSL of the column corresponding to column address signals CA0 to CAn, and column select gate 44 corresponding to this column select line CSL is rendered conductive.
Thus, the write data from selector 34 is provided to bit line pair BL and /BL of the selected column via data input/output line pair IO and /IO. The write data is provided as a potential difference between bit lines BL and /BL. Then, row decoder 47 raises to the selected level or the "H" level word line WL of the row corresponding to row address signals RA0 to RAn, and an N-channel MOS transistor of a memory cell MC in the row is rendered conductive. The capacitor of a selected memory cell MC stores the charge of an amount corresponding to the potential of bit line BL or /BL.
During the read operation, first, bit line equalizing signal BLEQ falls to the "L" level, and the equalization of bit lines BL and /BL is interrupted. Then, row decoder 47 raises to the selected level or the "H" level word line WL of the row corresponding to row address signals RA0 to RAn. The potentials of bit lines BL and /BL slightly change according to the amount of charge of the capacitor in the activated memory cell MC.
Then, sense amplifier activating signals SON and ZSOP respectively attain the "H" level and the "L" level, activating sense amplifier 45. When the potential of bit line BL is slightly higher than the potential of bit line /BL, the potential of bit line BL is pulled up to the "H" level, and the potential of bit line /BL is pulled down to the "L" level. Conversely, when the potential of bit line /BL is slightly higher than the potential of bit line BL, the potential of bit line /BL is pulled up to the "H" level, and the potential of bit line BL is pulled down to the "L" level.
Then, row decoder 48 raises to the selected level or the "H" level column select line CSL of the column corresponding to column address signals CA0 to CAn, rendering column select gate 44 of the column conductive. Data on bit line pair BL and /BL of the selected column is provided to selector 34 via column select gate 44 and data input/output line pair IO and /IO. The arrangement and the operation of other memory blocks 33b to 33d are the same as memory blocks 33a.
Referring back to FIG. 9, selector 34 provides write data DI to each of four memory blocks 33a to 33d when a test signal TE10 is at the active level or the "H" level. Selector 34 selects one of four memory blocks 33a to 33d according to block selecting signals B0 and B1 when test signal TE10 is at the inactive level or the "L" level, and provides read data DO from the selected memory block to selector 40 during a read operation, and provides write data DI to the selected memory block during a write operation. Test signal TE10 attains the active level or the "H" level during a test, and attains the inactive level or the "L" level during a normal operation. Data input buffer 35 transmits to selector 34 write data DI provided via a data input/output terminal T0 from outside, according to a write enable signal ZWE attaining the active level or the "L" level.
Comparison data register 36 latches comparison data DC provided from outside via data input/output terminal T0 and provides comparison data DC to determination circuit 37 according to a latch signal LDC attaining the active level or the "H" level. Determination circuit 37 causes a determination signal JD to attain the "H" level when four bits of data read out from memory portion 33 and comparison data DC all match, and causes determination signal JD to attain the "L" level when they do not match.
Gate circuit 38 inverts determination signal JD generated by determination circuit 37 and provides the inverted signal to a set terminal S of determination result register 39 according to a gate signal GT attaining the active level or the "H" level. When gate signal GT is at the active level or the "H" level, determination circuit 37 and gate circuit 38 are represented by one 5-input EX-OR gate 49, as shown in FIG. 11.
Determination result register 39 causes a determination signal JDO to attain the "L" level according to a reset signal RST attaining the active level or the "H" level, and causes determination signal JDO to attain the "H" level according to an output signal from gate circuit 38 attaining the "H" level. Determination result register 39 is formed by a flip-flop including two gate circuits 39a and 39b, as shown in FIG. 11.
Selector 40 includes a gate circuit 50, an AND gate 51, and an OR gate 52, as shown in FIG. 12. When test signal TE10 is at the active level or the "H" level, output signal JDO from register 39 passes through AND gate 51 and OR gate 52, and when test signal TE10 is at the inactive level or the "L" level, read data DO from selector 34 passes through gate circuit 50 and OR gate 52. Data output buffer 41 transmits to the outside data signal DO and signal JDO from selector 40 via data input/output terminal T0 according to an output enable signal ZOE attaining the active level or the "L" level. Moreover, the portion of DRAM 30 shown in FIG. 9 excluding address buffer circuit 31 and control signal generating circuit 32, i.e., the portion enclosed by the dotted lines, is provided in plurality (for instance, four).
Now, the operation of DRAM 30 shown in FIGS. 9 to 12 will be described. During a normal write operation, write data DI provided from outside is provided to selector 34 via data input buffer 35. Selector 34 selects one of four memory blocks 33a to 33d, row decoder 47 and column decoder 48 select one memory cell MC of a plurality of memory cells MC belonging to the selected memory block, and write data DI is written into the selected memory cell MC.
During a normal read operation, in each of the four memory blocks 33a to 33d, row decoder 47 and column decoder 48 select one memory cell MC out of a plurality of memory cells MC belonging to the memory block, and the data of the selected memory cell MC is read out. Selector 34 selects one of four bits of read data, and the selected read data DO is output to the outside via selector 40 and data output buffer 41.
As shown in FIG. 13, during a test, a plurality (twelve in the figure) of DRAMs 30 are arranged in a matrix of rows (three rows in the figure) and columns (four columns in the figure) on one burn-in test board 55. Drivers 61a to 61c for inputting of control signals /CS0 to /CS2 are respectively provided to the three rows of DRAMs 30, and drivers 62a to 62d for inputting write data DI0 to DI3 and drivers 63a to 63d for outputting determination signals JDO0 to JDO3 are respectively provided to four columns of DRAMs 30. These drivers 61a to 61c, 62a to 62d, and 63a to 63d are provided within a tester (not shown). In practice, drivers for inputting address signals A0 to An, drivers for inputting control signals /RAS, /CAS, /WE, and /OE, and a driver for inputting a clock signal CLK are commonly provided to all DRAMs 30 on board 55, which are not shown in order to simplify the drawing.
During a write operation in a test, signals /CS0 to /CS2 are all brought to the active level or the "L" level, activating all DRAMs 30 on board 55, while signal TE10 attains the active level or the "H" level. In each DRAM 30, write data DI from the tester is provided to four memory blocks 33a to 33d via data input buffer 35 and selector 34. In each memory block, write data DI from selector 34 is written into memory cell MC of the address designated by address signals A0 to An. Therefore, the same data is written into four memory cells MC at the same time. Every address of each DRAM 30 is successively designated in a prescribed cycle, and data DI of a prescribed logic level is written into each address.
During a read operation in a test, signals /CS0 to /CS2 are all brought to the active level or the "L" level, activating all DRAMs 30 on board 55. First, a latch signal LDC is brought to the active level or the "H" level, while comparison data DC is provided from outside and is latched into comparison data register 36. Comparison data DC has the same logic level as the data to be read from memory cell MC of the address for the next read operation, i.e., the data written into that memory cell MC. Moreover, reset signal RST is brought to the "H" level in a pulsed manner, thereby resetting determination result register 39 and bringing signal JDO to the "L" level. Further, test signal TE10 is brought to the active level or the "H" level.
Then, the address for which a read operation is to performed is designated by address signals A0 to An, and four bits of data is read out from memory portion 33 in each DRAM 30. When the logic levels of these four bits of data and comparison data DC all match, signal JD attains the "H" level. When they do not match, signal JD attains the "L" level. Thereafter, signal GT attains the active level or the "H" level, and signal JD is inverted and provided to set terminal S of determination result register 39. Output signal JDO from register 39 attains the "L" level when the above five bits of data match, and attains the "H" level when they do not match. Moreover, comparison data DC is introduced in order to prevent the mistake of four memory cells MC being determined as normal when the four bits of data read out from memory portion 33 are all the inverted data of the write data. Then, signals /CS0 to /CS2 are temporarily brought to the inactive level or the "L" level, and all DRAMs 30 on board 55 enter the standby state.
Then, signal /CS0 is first brought to the active level or the "L" level, activating four DRAMs 30 in the first row, and output enable signal ZOE is brought to the active level or the "L" level. Determination signal JDO in each of four DRAMs 30 in the first row is output to the tester via data output buffer 41. At this time, at least one of four memory cells MC of DRAM 30 whose signal JDO is at the "H" level is determined as being defective. Thereafter, signals /CS1 and /CS2 are successively brought to the active level or the "L" level, and determination signals JDO of DRAMs 30 in each row are provided to the tester, whereby memory cells MC of each DRAM 30 are determined as being normal or not. Thus, the normalcy of all memory cells MC of each DRAM 30 is determined, four memory cells MC at a time. A defective memory cell MC is replaced by a spare memory cell (not shown).
Since selector 40 is provided in a conventional DRAM 30, read data DO is delayed by selector 40, resulting in the problem of a slower access speed.
In addition, since comparison data register 36 is provided, the load capacitance of data input/output terminal T0 is made larger, which also leads to a slower access speed.
Moreover, in a conventional testing method, a plurality of DRAMs 30 are mounted on one test board 55, and the data write/read operations for all DRAMs 30 are performed simultaneously. Too large a number of DRAMs 30 causes the temperature of test board 55 to exceed the maximum tolerable value and causes the consumed current during the test to exceed the maximum tolerable value for the tester so that an accurate test cannot be conducted.